Failure analysis at die level with highly-precise, selective de-layering of single chip layers
Possible applications:
- Assurance of design and process quality
- Monitoring and evaluation of selected die layers
- Gaining basic information for the optimization of the die layout
- Failure analysis at die level
Reverse chip preparation according to HTV - DIE-Layering® Method
For exact process control and diagnostics at die level the analysis of internal chip layers is performed according to the DIE-layering® method, developed by HTV.
Single layers of the die are etched with high precision from passivation to the selected die layer by using specific etching methods in a unique combinatorics. In the next step analysis and evaluation of exposed structures takes place with the scanning electron microscope (SEM).
Hence, detailed conclusions are obtained for the process optimization, for example at wafer production, or manufacturing defects are quickly recognized in case of atypical components already assembled.